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1module dma_ctrl #(
2  parameter ADDR_W = 32,
3  parameter DATA_W = 128
4) (
5  input  wire              aclk,
6  input  wire              aresetn,
7  input  wire [ADDR_W-1:0] awaddr,
8  input  wire              awvalid,
9  output wire              awready
10);
11 
12  // Write-1-to-clear error flag
13  always @(posedge aclk or negedge aresetn)
14    if (!aresetn)      err_q <= 1'b0;
15    else if (wr_err)   err_q <= 1'b1;
16    else if (w1c_err)  err_q <= 1'b0;
17 
18endmodule

− localparam FIFO_DEPTH = 16;
+ localparam FIFO_DEPTH = 32;
   localparam FIFO_W     = DATA_W;
  
− assign awready = !fifo_full;
+ // Backpressure one cycle early to close timing at 1.2 GHz
+ assign awready = !fifo_almost_full;