React IP Core Card
The catalog entry for licensable IP — a different animal from a sellable part: versioned (v2.4.1), qualified by maturity (SILICON-PROVEN / PRODUCTION / BETA), described by its bus interfaces and process nodes as mono chips, quantified by a gate-count/power stat grid, and sold on its deliverables checklist (RTL, UVM environment, IP-XACT registers…). Doc links and an action slot close the card. This is what an IP vendor's product grid is made of.
DMA Engine — 8ch scatter-gather
v2.4.1Descriptor-based DMA with per-channel arbitration and W1C error reporting.
Bus
AXI4-128APB3
Nodes
16nm28nm40nm
Gate count412k
fmax1.2 GHz
Power18 mW/ch
Tape-outs7
- Synthesizable RTL (encrypted or plain)
- UVM environment + coverage model
- IP-XACT register map
- Integration + timing constraints
PCIe Gen4 PHY — x4
v0.9.016 GT/s SerDes PHY with integrated reference clock and lane margining.
Bus
PIPE 5.2
Nodes
16nm
Area0.84 mm²
Power142 mW
- Hard macro (GDSII)
- Verification IP + compliance suite
- Signal-integrity report
Installation
npx shadcn@latest add ip-core-card.json
Usage
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Props
| Prop | Type | Default | Description |
|---|---|---|---|
| name | string | — | IP name |
| version | string | — | Semver, rendered vX.Y.Z in mono |
| maturity | 'silicon-proven' \ | 'production' \ | 'beta' |
| tagline | string | — | One-line description |
| buses | string[] | [] | Bus interface chips |
| nodes | string[] | [] | Qualified process nodes |
| stats | { label, value }[] | — | Mono stat grid (gates, power, tape-outs) |
| — | — | — | Checklist with check icons |
| — | — | — | Documentation links |
| — | — | — | Action slot |